With the growing diversity of semiconductor devices, the device characteristics also may become diverse. For example, devices in which logic devices or Central Processing Units (CPUs) are merged with Dynamic Random Access Memories (DRAMs) or Static Random Access Memories (SRAMs) are being developed and marketed. In such devices, gate oxide layers having different thicknesses may be formed within a single chip in order to maintain each of the characteristics of the merged devices. Thus, a dual gate oxide layer composed of two different thicknesses or a multiple gate oxide layer composed of three or more thicknesses may be used.
Furthermore, gate oxide layers having different thicknesses may be formed in a single chip in order to vary an operating voltage in a device. For example, a gate oxide layer formed in an area in which an NMOS transistor is to be formed may be thicker than a gate oxide layer formed in an area in which a PMOS transistor is to be formed. Also, a gate oxide layer formed in a peripheral circuit area of a DRAM may be thicker than a gate oxide layer formed in a cell area of the DRAM.
As the integration density of semiconductor devices increases, gate oxide layers may be further scaled. Even though the thickness of the gate oxide layers may become thinner due to scaling, good electrical characteristics may need to be maintained. However, as the thickness of the gate oxide layers becomes thinner, a leakage current due to direct tunneling may increase, which may cause an increase in a standby current, the disturbance of a logic state, the deterioration of Time Dependent Dielectric Breakdown (TDDB) characteristics and/or other undesirable characteristics.
Accordingly, as is well known in the prior art, leakage current may be reduced by subjecting gate oxide layers to plasma nitridation. This plasma nitridation is performed to reduce the leakage current, to reduce the depletion of a polysilicon gate, to prevent boron (B) from penetrating the gate oxide layers from a gate doped with boron and/or for other purposes.
Plasma nitridation can generally achieve the above goals in a thin gate oxide layer having a thickness of 25 Å or less. However, when a dual gate oxide layer or a multiple gate oxide layer is to be formed, after plasma nitridation, leakage current may increase in a thick gate oxide layer that is formed to a thickness of 35 Å or more along with a thin gate oxide layer. In particular, a charge-to-breakdown (Qbd) value may be reduced to the level of 1/10or less of the value prior to plasma nitridation. Thus, the reliability of the thick gate oxide layer may be very seriously deteriorated.
FIG. 1 is a graph illustrating variations in leakage current flowing through a thick gate oxide layer (40 Å) of an NMOS transistor after plasma nitridation. In FIG. 1, the horizontal axis and the vertical axis denote a gate voltage Vg and a gate leakage current density Jg, respectively. Curve (a), marked with a solid line, represents the density of leakage current flowing through a gate oxide layer formed using Rapid Thermal Oxidation (RTO). Leakage current flowing through the gate oxide layer after undergoing Remote Plasma Nitridation (RPN) is marked with (b). Curve (c), marked with a one-dot chain line, denotes the density of leakage current flowing through the gate oxide layer after undergoing Decoupled Plasma Nitridation (DPN).
Where a thin gate oxide layer having a thickness of about 20 Å undergoes RPN or DPN, the density of leakage current flowing through the thin gate oxide layer may decrease. However, in a case of a thick gate oxide layer having a thickness of about 40 Å, as seen in FIG. 1, the density of leakage current flowing through the thick gate oxide layer increases after RPN (b) and DPN (c). This phenomenon may be attributed to the formation of SiON due to incorporated nitrogen atoms when the thick gate oxide layer undergoes nitridation, which may result in a reduction in a band gap and an increase in electron trap sites.
In addition, as seen in FIG. 2, the Qbd value decreases in the thick gate oxide layer due to nitridation. FIG. 2 is a graph illustrating the Qbd value of the thick gate oxide layer measured before and after plasma nitridation. In FIG. 2, the horizontal axis and the vertical axis denote the Qbd value and a conventional Weibull distribution value, respectively. In other words, the vertical axis denotes cumulative failures. The current density J of the thick gate oxide layer is 0.005 A/cm2 and the area of the thick gate oxide layer is 120000 μm2.
Referring to FIG. 2, the Qbd value of the thick gate oxide layer after RPN (marked with black circles) and DPN (marked with black triangles) is reduced to 1/10or less of the Qbd value of the thick gate oxide layer before plasma nitridation (marked with black squares). This appears to be because the electron trap sites are created due to silicon dangling bonds, bivalent nitrogen bonds and/or the like generated during plasma nitridation and then injected electrons are trapped in the electron trap sites, which may increase an intensity of a local electrical field, thereby causing a dielectric breakdown.
Ordinarily, an increase in the leakage current flowing through the thick gate oxide layer after plasma nitridation may not be considered a big problem. However, as shown in FIG. 2, the deterioration of the reliability of the thick gate oxide layer, represented by a reduction in the Qbd value, may not allow the application of plasma nitridation in the device, and thus may be very problematic. Therefore, reducing or preventing deterioration of the reliability of the thick gate oxide layer after plasma nitridation may be an important factor of determining whether plasma nitridation can actually be applied to a dual or a multiple gate oxide layer.